View ISPLSI2128VL-100LB100_86631.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ispLSI 2128VL
2.5V In-System Programmable SuperFASTTM High Density PLD Features
* SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC 6000 PLD Gates 128 and 64 I/O Pin Versions, Eight Dedicated Inputs 128 Registers High Speed Global Interconnect Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. -- Small Logic Block Size for Random Logic -- 100% Functional, JEDEC and Pinout Compatible with ispLSI 2128V and 2128VE Devices * 2.5V LOW VOLTAGE 2128 ARCHITECTURE -- Interfaces with Standard 3.3V Devices (Inputs and I/Os are 3.3V Tolerant) -- 125 mA Typical Active Current * HIGH PERFORMANCE E2CMOS(R) TECHNOLOGY -- -- -- -- -- -- -- -- -- -- --
(R)
Functional Block Diagram*
Output Routing Pool (ORP) D7 D6 D5 D4 Output Routing Pool (ORP) D3 D2 D1 D0 C7
Output Routing Pool (ORP)
A0
A1
C6
A2
D
Q
C5
A3
D
Q
C4
Output Routing Pool (ORP)
A4
D
Q
GLB
C3
A5
D Q
C2
A6
C1
A7 B0 B1
Global Routing Pool (GRP)
B2 B3 B4 B5 B6 B7
C0
fmax = 150 MHz Maximum Operating Frequency tpd = 6.0 ns Propagation Delay
Electrically Erasable and Reprogrammable Non-Volatile 100% Tested at Time of Manufacture Unused Product Term Shutdown Saves Power
Output Routing Pool (ORP)
Output Routing Pool (ORP)
*128 I/O version shown
CLK 0 CLK 1 CLK 2
0139A/2128VL
Description
The ispLSI 2128VL is a High Density Programmable Logic Device available in 128 and 64 I/O-pin versions. The device contains 128 Registers, eight Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2128VL features in-system programmability through the Boundary Scan Test Access Port (TAP) and is 100% IEEE 1149.1 Boundary Scan Testable. The ispLSI 2128VL offers nonvolatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 2128VL device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. D7 (see Figure 1). There are a total of 32 GLBs in the ispLSI 2128VL device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device.
* IN-SYSTEM PROGRAMMABLE -- 2.5V In-System Programmability (ISPTM) Using Boundary Scan Test Access Port (TAP) -- Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of WiredOR Bus Arbitration Logic -- Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality -- Reprogram Soldered Devices for Faster Prototyping * 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE * THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS -- -- -- -- -- -- Enhanced Pin Locking Capability Three Dedicated Clock Input Pins Synchronous and Asynchronous Clocks Programmable Output Slew Rate Control Flexible Pin Placement Optimized Global Routing Pool Provides Global Interconnectivity
* ispDesignEXPERTTM - LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING -- Superior Quality of Results -- Tightly Integrated with Leading CAE Vendor Tools -- Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZERTM -- PC and UNIX Platforms
Copyright (c) 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
September 2000
2128vL_02
1
Output Routing Pool (ORP)
Logic Array
Output Routing Pool (ORP)
Specifications ispLSI 2128VL
Functional Block Diagram
Figure 1. ispLSI 2128VL Functional Block Diagram (128-I/O and 64-I/O Versions)
I/O 127 I/O 126 I/O 125 I/O 124 I/O 123 I/O 122 I/O 121 I/O 120 I/O 119 I/O 118 I/O 117 I/O 116 I/O 115 I/O 114 I/O 113 I/O 112 I/O 111 I/O 110 I/O 109 I/O 108 I/O 107 I/O 106 I/O 105 I/O 104 I/O 103 I/O 102 I/O 101 I/O 100 I/O 99 I/O 98 I/O 97 I/O 96 I/O 63 I/O 62 I/O 61 I/O 60 I/O 59 I/O 58 I/O 57 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48 IN 7* IN 6* IN 7 IN 6
RESET GOE 0 GOE 1 Input Bus
RESET GOE 0 GOE 1 Megablock Input Bus
Output Routing Pool (ORP)
Megablock
Generic Logic Blocks (GLBs)
Output Routing Pool (ORP)
D4 D3 D2 D1 D0 IN 5 IN 4 C7 I/O 95 I/O 94 I/O 93 I/O 92 I/O 91 I/O 90 I/O 89 I/O 88 I/O 87 I/O 86 I/O 85 I/O 84 I/O 83 I/O 82 I/O 81 I/O 80 I/O 79 I/O 78 I/O 77 I/O 76 I/O 75 I/O 74 I/O 73 I/O 72 I/O 71 I/O 70 I/O 69 I/O 68 I/O 67 I/O 66 I/O 65 I/O 64
Output Routing Pool (ORP)
Generic Logic Blocks (GLBs)
D7
D6
D5
D7
D6
D5
D4
D3
D2
D1
D0
IN 5* IN 4* C7 I/O 47 I/O 46 I/O 45 I/O 44
I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 TDI/IN 0 TMS/IN 1
Output Routing Pool (ORP)
I/O 0 I/O 1 I/O 2 I/O 3
Output Routing Pool (ORP)
A0 C6
I/O 0 I/O 1 I/O 2 I/O 3
A0 C6
A1 C5
A1 C5 I/O 4 I/O 5 I/O 6 I/O 7
A2
A2
A3
Input Bus
Output Routing Pool (ORP)
C3
Input Bus
Output Routing Pool (ORP)
Global Routing Pool (GRP)
C4
Input Bus
A3
Global Routing Pool (GRP)
C4
Output Routing Pool (ORP)
I/O 43 I/O 42 I/O 41 I/O 40
C3
Input Bus
A4
A4 C2
Output Routing Pool (ORP)
C2
A5 C1
I/O 8 I/O 9 I/O 10 I/O 11
I/O 39 I/O 38 I/O 37 I/O 36
A5 C1 I/O 35 I/O 34 I/O 33 I/O 32
A6 C0
A6 C0 I/O 12 I/O 13 I/O 14 I/O 15 TDI/IN 0 TMS/IN 1
A7
A7
B0
B1
B2
B3
B4
B5
B6
B7
CLK 0 CLK 1 CLK 2
B0
B1
B2
B3
B4
B5
B6
B7
Output Routing Pool (ORP)
Input Bus BSCAN
TDO/IN 2 TCK/IN 3 I/O 32 I/O 33 I/O 34 I/O 35 I/O 36 I/O 37 I/O 38 I/O 39 I/O 40 I/O 41 I/O 42 I/O 43 I/O 44 I/O 45 I/O 46 I/O 47
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Input Bus BSCAN
I/O 16 I/O 17 I/O 18 I/O 19
I/O 20 I/O 21 I/O 22 I/O 23
I/O 24 I/O 25 I/O 26 I/O 27
I/O 48 I/O 49 I/O 50 I/O 51
I/O 52 I/O 53 I/O 54 I/O 55
I/O 56 I/O 57 I/O 58 I/O 59
I/O 60 I/O 61 I/O 62 I/O 63
TDO/IN 2 TCK/IN 3
I/O 28 I/O 29 I/O 30 I/O 31
Y0 Y1 Y2
0139B/2128VL
Y0 Y1 Y2
CLK 0 CLK 1 CLK 2
0139B/2128VL.64IO
*Not available on 84-PLCC Device
The 128-I/O 2128VL contains 128 I/O cells, while the 64I/O version contains 64 I/O cells. Each I/O cell is directly connected to an I/O pin and can be individually programmed to be a combinatorial input, output or bi-directional I/O pin with 3-state control, and the output drivers can source 4mA or sink 8mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. Device pins can be safely driven to 3.3V signal levels to support mixed-voltage systems. Eight GLBs, 32 or 16 I/O cells, two dedicated inputs and two or one ORPs are connected together to make a Megablock (see Figure 1). The outputs of the eight GLBs are connected to a set of 32 or 16 universal I/O cells by the two or one ORPs. Each ispLSI 2128VL device contains four Megablocks. The GRP has as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI 2128VL device are selected using the dedicated clock pins. Three dedicated clock pins (Y0, Y1, Y2) or an asynchronous clock can be selected on a
GLB basis. The asynchronous or Product Term clock can be generated in any GLB for its own clock. Programmable Open-Drain Outputs In addition to the standard output configuration, the outputs of the ispLSI 2128VL are individually programmable, either as a standard totem-pole output or an open-drain output. The totem-pole output drives the specified Voh and Vol levels, whereas the open-drain output drives only the specified Vol. The Voh level on the open-drain output depends on the external loading and pull-up. This output configuration is controlled by a programmable fuse. The default configuration is a totem-pole configuration. The open-drain/totem-pole option is selectable through the ispDesignEXPERT software tools.
2
Specifications ispLSI 2128VL
Absolute Maximum Ratings 1
Supply Voltage Vcc ................................ -0.5 to +4.05V Input Voltage Applied ............................. -0.5 to +4.05V Off-State Output Voltage Applied .......... -0.5 to +4.05V Storage Temperature ................................ -65 to 150C Case Temp. with Power Applied .............. -55 to 125C Max. Junction Temp. (TJ) with Power Applied ... 150C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
SYMBOL PARAMETER Supply Voltage Input Low Voltage Input High Voltage Commercial Industrial TA = 0C to + 70C TA = -40C to + 85C MIN. 2.3 2.3 -0.3 1.7 MAX. 2.7 2.7 0.7 3.6 UNITS V V V V
VCC VIL VIH
Table 2-0005/2128VL
Capacitance (TA=25C, f=1.0 MHz)
SYMBOL PARAMETER Dedicated Input Capacitance I/O Capacitance Clock and Global Output Enable Capacitance TYPICAL 8 6 10 UNITS pf pf pf TEST CONDITIONS VCC = 2.5V, VIN = 0.0V VCC = 2.5V, VI/O = 0.0V VCC = 2.5V, VY = 0.0V
Table 2-0006/2128VL
C1 C2 C3
Erase Reprogram Specifications
PARAMETER Erase/Reprogram Cycles MINIMUM 10,000 MAXIMUM - UNITS Cycles
Table 2-0008/2128VL
3
Specifications ispLSI 2128VL
Switching Test Conditions
Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load
3-state levels are measured 0.15V from steady-state active level.
GND to VCC 1.5ns 10% to 90% VCC/2 VCC/2 See Figure 2
Table 2 - 0003/2128VL
Figure 2. Test Load
VCC R1 Device Output R2 CL* Test Point
Output Load Conditions (see Figure 2)
TEST CONDITION A B Active High Active Low Active High to Z at VOH -0.15V Active Low to Z at VOL +0.15V R1 250 R2 218 218 CL 35pF 35pF 35pF 5pF 5pF
250
*CL includes Test Fixture and Probe Capacitance.
0213A/2128VL
218
250
C
Table 2-0004/2128VL
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL PARAMETER Output Low Voltage CONDITION IOL = 100A IOL = 8mA IOH = -100A Output High Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current BSCAN Input Pull-Up Current I/O Active Pull-Up Current Output Short Circuit Current Operating Power Supply Current IOH = -1mA IOH = -4mA 0V VIN VIL (Max.) VIH (min) VIN 3.6V 0V VIN VIL 0V VIN VIL VCC = 2.5V, VOUT = 0.5V VIL = 0.0V, VIH = 2.5V fCLK = 1 MHz
Table 2-0007/2128VL 1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2. Measured using eight 16-bit counters. 3. Typical values are at VCC = 2.5V and TA = 25C. 4. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to Power Consumption section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum ICC. 5. With no pull-up resistors.
MIN. -- --
VCC - 0.2
TYP. -- -- -- -- -- -- -- -- -- -- 125
3
MAX. UNITS 0.2 0.4 -- -- -- -10 10 -150 -150 -100 -- V V V V V A A A A mA mA
VOL VOH IIL IIH IIL-isp IIL-PU IOS1 ICC2, 4
5
2.0 1.8 -- -- -- -- -- --
4
Specifications ispLSI 2128VL
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER TEST COND. A A A -- -- -- A -- -- A -- A -- B C B C -- --
3
# 1 2 3 4 5 6 7 8 9
DESCRIPTION
1
-150 -- --
2 1
-135 -- -- 135 95 143 5.0 -- 0.0 6.0 -- 0.0 -- 5.5 -- -- -- -- 3.5 3.5 7.5 10.0 -- -- -- -- 4.5 -- -- 5.5 -- 8.0 -- 12.0 12.0 7.0 7.0 -- --
-100 -- -- 100 77 100 6.5 -- 0.0 8.0 -- 0.0 -- 6.5 -- -- -- -- 5.0 5.0 10.0 13.0 -- -- -- -- 5.0 -- -- 6.0 -- 13.5 -- 15.0 15.0 9.0 9.0 -- --
MIN. MAX. MIN. MAX. MIN. MAX. 6.0 8.5 -- -- -- -- 4.0 -- -- 5.0 -- 6.0 -- 10.0 10.0 6.0 6.0 -- --
UNITS ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tpd1 tpd2 fmax fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl
Data Propagation Delay, 4PT Bypass, ORP Bypass Data Propagation Delay Clock Frequency with Internal Feedback Clock Frequency, Max. Toggle GLB Reg. Setup Time before Clock, 4 PT Bypass GLB Reg. Clock to Output Delay, ORP Bypass GLB Reg. Hold Time after Clock, 4 PT Bypass GLB Reg. Setup Time before Clock Clock Frequency with External Feedback ( tsu2 + tco1)
150 111 166 4.0 -- 0.0 5.0 -- 0.0 -- 5.0 -- -- -- -- 3.0 3.0
10 GLB Reg. Clock to Output Delay 11 GLB Reg. Hold Time after Clock 12 Ext. Reset Pin to Output Delay, ORP Bypass 13 Ext. Reset Pulse Duration 14 Input to Output Enable 15 Input to Output Disable 16 Global OE Output Enable 17 Global OE Output Disable 18 External Synchronous Clock Pulse Duration, High 19 External Synchronous Clock Pulse Duration, Low
1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock. 2. Standard 16-bit counter using GRP feedback. 3. Reference Switching Test Conditions section.
Table 2-0030/2128VL
5
Specifications ispLSI 2128VL
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAMETER Inputs #
2
DESCRIPTION
-150
-135
-100
MIN. MAX. MIN. MAX. MIN. MAX. -- -- -- -- -- -- -- -- -- 1.2 2.8 -- -- -- -- 1.2 -- -- -- -- -- -- -- 1.7 1.9 -- 0.4 1.5 1.1 2.5 3.0 4.0 4.0 4.0 0.0 -- -- 0.3 0.6 4.9 5.0 4.2 1.4 0.4 1.6 2.0 3.5 3.5 2.5 1.7 1.9 3.4 -- -- -- -- -- -- -- -- -- 1.7 3.3 -- -- -- -- 2.1 -- -- -- -- -- -- -- 2.1 2.3 -- 1.0 2.2 1.2 3.2 3.2 4.2 4.2 4.2 0.5 -- -- 0.3 1.1 6.6 5.8 4.5 1.5 0.5 1.6 2.0 4.0 4.0 3.0 2.1 2.3 4.8 -- -- -- -- -- -- -- -- -- 1.7 4.8 -- -- -- -- 2.8 -- -- -- -- -- -- -- 2.6 2.8 -- 0.9 2.7 1.8 5.2 4.7 6.2 6.2 6.2 1.0 -- -- 0.3 4.3 8.9 7.4 4.8 1.5 0.5 1.6 2.0 4.9 4.9 4.1 2.6 2.8 7.1
UNITS
tio tdin
GRP
20 Input Buffer Delay 21 Dedicated Input Delay 22 GRP Delay 23 4 Product Term Bypass Path Delay (Combinatorial) 24 4 Product Term Bypass Path Delay (Registered) 25 1 Product Term/XOR Path Delay 26 20 Product Term/XOR Path Delay 27 XOR Adjacent Path Delay 3 28 GLB Register Bypass Delay 29 GLB Register Setup Time before Clock 30 GLB Register Hold Time after Clock 31 GLB Register Clock to Output Delay 32 GLB Register Reset to Output Delay 33 GLB Product Term Reset to Register Delay 34 GLB Product Term Output Enable to I/O Cell Delay 35 GLB Product Term Clock Delay 36 ORP Delay 37 ORP Bypass Delay 38 Output Buffer Delay 39 Output Slew Limited Delay Adder 40 I/O Cell OE to Output Enabled 41 I/O Cell OE to Output Disabled 42 Global Output Enable 43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 44 Clock Delay, Y1 or Y2 to Global GLB Clock Line 45 Global Reset to GLB
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tgrp
GLB
t4ptbpc t4ptbpr t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck
ORP
torp torpbp
Outputs
tob tsl toen todis tgoe
Clocks
tgy0 tgy1/2
Global Reset
tgr
1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros.
Table 2-0036/2128VL
6
Specifications ispLSI 2128VL
ispLSI 2128VL Timing Model
I/O Cell GRP Feedback Ded. In Comb 4 PT Bypass #23 GRP #22 Reg 4 PT Bypass #24 20 PT XOR Delays #25, 26, 27 Reset #45 D RST #29, 30, 31, 32 GLB Reg Bypass #28 GLB Reg Delay Q ORP Bypass #37 ORP Delay #36 #38, 39 I/O Pin (Output) GLB ORP I/O Cell
#21 I/O Delay #20
I/O Pin (Input)
Control RE PTs OE #33, 34, CK 35 Y0,1,2 GOE 0 #43, 44 #42
#40, 41
0491/2032
Derivations of tsu, th and tco from the Product Term Clock tsu
= = = 4.0ns = = = = 3.0ns = = = = 9.0ns = Logic + Reg su - Clock (min) (tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min)) (#20 + #22 + #26) + (#29) - (#20 + #22 + #35) (0.4 + 1.1 + 4.0) + (1.2) - (0.4 + 1.1 + 1.2) Clock (max) + Reg h - Logic (tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor) (#20 + #22 + #35) + (#30) - (#20 + #22 + #26) (0.4 + 1.1 + 4.2) + (2.8) - (0.4 + 1.1 + 4.0) Clock (max) + Reg co + Output (tio + tgrp + tptck(max)) + (tgco) + (torp + tob) (#20 + #22 + #35) + (#31) + (#36 + #38) (0.4 + 1.1 + 4.2) + (0.3) + (1.4 + 1.6)
th
tco
Note: Calculations are based upon timing specifications for the ispLSI 2128VL-150L.
Table 2-0042/2128VL
7
Specifications ispLSI 2128VL
Power Consumption
Power consumption in the ispLSI 2128VL device depends on two primary factors: the speed at which the device is operating and the number of Product Terms Figure 3. Typical Device Power Consumption vs fmax
200
used. Figure 3 shows the relationship between power and operating speed.
ispLSI 2128VL
180 160 140 120 100
0 25 50 75 100 125 150
ICC (mA)
fmax (MHz)
Notes: Configuration of eight 16-bit counters Typical current at 2.5V, 25 C
ICC can be estimated for the ispLSI 2128VL using the following equation: ICC = 12 + (# of PTs * 0.46) + (# of nets * max freq * 0.0029)
Where: # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max freq = Highest Clock Frequency to the device (in MHz) The ICC estimate is based on typical conditions (VCC = 2.5V, room temperature) and an assumption of two GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified.
0127/2128VL
8
Specifications ispLSI 2128VL
Signal Descriptions
Signal Name RESET GOE 0, GOE1 Y0, Y1, Y2 BSCAN TDI/IN 0 TCK/IN 3 TMS/IN 1 TDO/IN 2 IN 4 - IN 7 GND VCC NC1 I/O Global Output Enable input pins. Dedicated Clock Input - These clock inputs are connected to one of the clock inputs of all the GLBs in the device. Input - Dedicated in-system programming Boundary Scan enable input pin. This pin is brought low to enable the programming mode. The TMS, TDI, TDO and TCK controls become active. Input - This pin performs two functions. When BSCAN is logic low, it functions as a serial data input pin to load programming data into the device. When BSCAN is high, it functions as a dedicated input pin. Input - This pin performs two functions. When BSCAN is logic low, it functions as a clock pin for the Boundary Scan state machine. When BSCAN is high, it functions as a dedicated input pin. Input - This pin performs two functions. When BSCAN is logic low, it functions as a mode control pin for the Boundary Scan state machine. When BSCAN is high, it functions as a dedicated input pin. Output/Input - This pin performs two functions. When BSCAN is logic low, it functions as an output pin to read serial shift register data. When BSCAN is high, it functions as a dedicated input pin. Dedicated Input Pins to the device. Ground (GND) Vcc No Connect Input/Output Pins - These are the general purpose I/O pins used by the logic array. Description Active Low (0) Reset pin resets all the registers in the device.
1. NC pins are not to be connected to any active signals, VCC or GND.
9
Specifications ispLSI 2128VL
Signal Locations
Signal RESET GOE 0, GOE 1 Y0, Y1, Y2 BSCAN TDI/IN 0 TCK/IN 3 TMS/IN 1 TDO/IN 2 IN 4 - IN 7 GND 208-Ball fpBGA H3 J16, H1 H2, H14, J14 J1 J3 J15 P8 C9 H16, A9, T8, H4 D4, D13, G7, G8, G9, G10, H7, H8, H9, H10, J7, J8, J9, J10, K7, K8, K9, K10, N4, N13 D5, D6, D12, E4, E13, F4, F13, L4, L13, M4, M13, N5, N11, N12 A2, A3, A15, A16, B1, B2, B3, B14, B15, B16, C2, C3, C14, C15, D14, P1, P2, P3, P13, P14, P15, R1, R2, R3, R14, R15, R16, T1, T2, T15, T16 176-Pin TQFP 21 110, 23 20, 113, 108 25 26 107 66 154 114, 155, 67, 19 24, 46, 68, 87, 109, 134, 153, 175 160-Pin PQFP 19 100, 21 18, 103, 98 23 24 97 60 140 104, 141, 61, 17 22, 42, 62, 79, 99, 122, 139, 159 100-Ball caBGA D2 F9, E1 E3, F6, F8 E5 F2 G10 J5 B6 E9, A6, K5, D1 B7, F1, G9, K6 100-Pin TQFP 11 62, 13 10, 65, 60 15 16 59 37 87 66, 88, 38, 9 14, 39, 61, 86
VCC
2, 22, 43, 65, 90, 111, 131, 156
2, 20, 39, 59, 82, 101, 119, 142
A5, E2, F10, J4
12, 36, 63, 89
NC1
9, 18, 27, 36, 55, 64, 69, 78, 97, 106, 112, 115, 124, 143, 152, 157, 166
102
A8, C3, C4, D6, D8, E7, E10, F4, G3, G5, H7, H8, K3
4, 21, 25, 31, 44, 50, 54, 64, 71, 75, 81, 94, 100
1. NC pins are not to be connected to any active signals, VCC or GND.
10
Specifications ispLSI 2128VL
I/O Locations
Signal 208 fpBGA 176 TQFP 160 PQFP 100 caBGA 100 TQFP Signal 208 fpBGA 176 TQFP 160 PQFP 100 caBGA 100 TQFP
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 I/O 33 I/O 34 I/O 35 I/O 36 I/O 37 I/O 38 I/O 39 I/O 40 I/O 41 I/O 42 I/O 43 I/O 44 I/O 45 I/O 46 I/O 47 I/O 48 I/O 49 I/O 50 I/O 51 I/O 52 I/O 53 I/O 54 I/O 55 I/O 56 I/O 57 I/O 58 I/O 59 I/O 60 I/O 61 I/O 62 I/O 63
J2 J4 K1 K3 K2 K4 L1 L2 L3 M1 M2 M3 N1 N2 N3 P4 T3 R4 T4 P5 R5 N6 T5 R6 P6 T6 N7 R7 P7 T7 N8 R8 T9 P9 R9 N9 T10 P10 R10 N10 T11 P11 R11 T12 P12 R12 T13 R13 T14 N14 P16 N15 N16 M14 M15 M16 L15 L14 L16 K13 K15 K14 K16 J13
28 29 30 31 32 33 34 35 37 38 39 40 41 42 44 45 47 48 49 50 51 52 53 54 56 57 58 59 60 61 62 63 70 71 72 73 74 75 76 77 79 80 81 82 83 84 85 86 88 89 91 92 93 94 95 96 98 99 100 101 102 103 104 105
25 26 27 28 29 30 31 32 33 34 35 36 37 38 40 41 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 80 81 83 84 85 86 87 88 89 90 91 92 93 94 95 96
G1 F3 E4 H1 G2 J1 H2 K1 J2 K2 H3 J3 G4 H4 K4 H5 F5 J6 K7 H6 K8 G6 J7 K9 J8 K10 J9 J10 H9 H10 G7 G8 D10 E8 F7 C10 D9 B10 C9 A10 B9 A9 C8 B8 D7 C7 A7 C6 E6 B5 A4 C5 A3 D5 B4 A2 B3 A1 B2 B1 C2 C1 D4 D3
17 18 19 20 22 23 24 26 27 28 29 30 32 33 34 35 40 41 42 43 45 46 47 48 49 51 52 53 55 56 57 58 67 68 69 70 72 73 74 76 77 78 79 80 82 83 84 85 90 91 92 93 95 96 97 98 99 1 2 3 5 6 7 8
I/O 64 I/O 65 I/O 66 I/O 67 I/O 68 I/O 69 I/O 70 I/O 71 I/O 72 I/O 73 I/O 74 I/O 75 I/O 76 I/O 77 I/O 78 I/O 79 I/O 80 I/O 81 I/O 82 I/O 83 I/O 84 I/O 85 I/O 86 I/O 87 I/O 88 I/O 89 I/O 90 I/O 91 I/O 92 I/O 93 I/O 94 I/O 95 I/O 96 I/O 97 I/O 98 I/O 99 I/O 100 I/O 101 I/O 102 I/O 103 I/O 104 I/O 105 I/O 106 I/O 107 I/O 108 I/O 109 I/O 110 I/O 111 I/O 112 I/O 113 I/O 114 I/O 115 I/O 116 I/O 117 I/O 118 I/O 119 I/O 120 I/O 121 I/O 122 I/O 123 I/O 124 I/O 125 I/O 126 I/O 127
H15 H13 G16 G14 G15 G13 F16 F14 F15 E16 E14 E15 D16 C16 D15 A14 C13 B13 A13 C12 B12 D11 A12 C11 B11 D10 A11 B10 C10 D9 A10 B9 A8 C8 B8 D8 A7 C7 B7 D7 A6 C6 B6 A5 C5 B5 A4 B4 C4 A1 C1 D3 D2 D1 E3 E2 E1 F3 F2 F1 G4 G2 G3 G1
116 117 118 119 120 121 122 123 125 126 127 128 129 130 132 133 135 136 137 138 139 140 141 142 144 145 146 147 148 149 150 151 158 159 160 161 162 163 164 165 167 168 169 170 171 172 173 174 176 1 3 4 5 6 7 8 10 11 12 13 14 15 16 17
105 106 107 108 109 110 111 112 113 114 115 116 117 118 120 121 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 160 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
11
Specifications ispLSI 2128VL
Signal Configuration
ispLSI 2128VL 208-Ball fpBGA Signal Diagram
16 A B C D E F G H J K L M N P R T
NC1 NC1 I/O 77 I/O 76 I/O 73 I/O 70 I/O 66 IN 4
15
NC1 NC1 NC1 I/O 78 I/O 75 I/O 72 I/O 68 I/O 64
14
I/O 79 NC1 NC1 NC1 I/O 74 I/O 71 I/O 67 Y1 Y2 I/O 61 I/O 57 I/O 53 I/O 49 NC1 NC1 I/O 48
13
I/O 82 I/O 81 I/O 80
12
I/O 86 I/O 84 I/O 83
11
I/O 90 I/O 88 I/O 87 I/O 85
10
I/O 94 I/O 91 I/O 92 I/O 89
9
IN 5 I/O 95 TDO/ IN 2 I/O 93
8
I/O 96 I/O 98 I/O 97 I/O 99
7
I/O 100 I/O 102 I/O 101 I/O 103
6
I/O 104 I/O 106 I/O 105
5
I/O 107 I/O 109 I/O 108
4
I/O 110 I/O 111 I/O 112
3
NC1 NC1 NC1 I/O 115 I/O 118 I/O 121 I/O 126
RESET
2
NC1 NC1 NC1 I/O 116 I/O 119 I/O 122 I/O 125 Y0 I/O 0 I/O 4 I/O 7 I/O 10 I/O 13 NC1 NC1 NC1
1
I/O 113 NC1 I/O 114 I/O 117 I/O 120 I/O 123 I/O 127 GOE 1
BSCAN
A B C D E F G H J K L M N P R T
GND VCC VCC VCC I/O 69 I/O 65 I/O 63 I/O 59 VCC VCC GND NC1 I/O 47 I/O 46 VCC I/O 44 I/O 45 I/O 43
VCC VCC GND VCC VCC
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
I/O 124 IN 7 I/O 1 I/O 5 VCC VCC
GOE TCK/ 0 IN 3 I/O 62 I/O 58 I/O 55 I/O 52 I/O 50 NC1 NC1 I/O 60 I/O 56 I/O 54 I/O 51 NC1 NC1 NC1
TDI/ IN 0 I/O 3 I/O 8 I/O 11 I/O 14 NC1 NC1 I/O 16
I/O 2 I/O 6 I/O 9 I/O 12 NC1 NC1 NC1
ispLSI 2128VL
Bottom View
VCC I/O 41 I/O 42 I/O 40 I/O 39 I/O 37 I/O 38 I/O 36 I/O 35 I/O 33 I/O 34 I/O 32 I/O 30 TMS/ IN 1 I/O 31 IN 6 I/O 26 I/O 28 I/O 27 I/O 29 I/O 21 I/O 24 I/O 23 I/O 25
VCC GND I/O 19 I/O 20 I/O 22 I/O 15 I/O 17 I/O 18
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
208 BGA/2128VL
1. NCs are not to be connected to any active signals, Vcc or GND. Note: Ball A1 indicator dot on top side of package.
12
Specifications ispLSI 2128VL
Pin Configuration
ispLSI 2128VL 176-Pin TQFP Pinout Diagram
I/O 112 GND I/O 111 I/O 110 I/O 109 I/O 108 I/O 107 I/O 106 I/O 105 I/O 104 NC1 I/O 103 I/O 102 I/O 101 I/O 100 I/O 99 I/O 98 I/O 97 I/O 96 NC1 VCC IN 5 TDO/IN 2 GND NC1 I/O 95 I/O 94 I/O 93 I/O 92 I/O 91 I/O 90 I/O 89 I/O 88 NC1 I/O 87 I/O 86 I/O 85 I/O 84 I/O 83 I/O 82 I/O 81 I/O 80 GND I/O 79 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133
I/O 113 VCC I/O 114 I/O 115 I/O 116 I/O 117 I/O 118 I/O 119 1 NC I/O 120 I/O 121 I/O 122 I/O 123 I/O 124 I/O 125 I/O 126 I/O 127 1 NC IN 7 Y0 RESET VCC GOE 1 GND BSCAN TDI/IN 0 1 NC I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 1NC I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 VCC I/O 14
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
ispLSI 2128VL
Top View
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
I/O 78 VCC I/O 77 I/O 76 I/O 75 I/O 74 I/O 73 I/O 72 NC1 I/O 71 I/O 70 I/O 69 I/O 68 I/O 67 I/O 66 I/O 65 I/O 64 NC1 IN 4 Y1 NC1 VCC GOE 0 GND Y2 TCK/IN 3 NC1 I/O 63 I/O 62 I/O 61 I/O 60 I/O 59 I/O 58 I/O 57 I/O 56 NC1 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 VCC I/O 49
I/O 15 GND I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 NC1 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 NC1 VCC TMS/IN 1 IN 6 GND NC1 I/O 32 I/O 33 I/O 34 I/O 35 I/O 36 I/O 37 I/O 38 I/O 39 NC1 I/O 40 I/O 41 I/O 42 I/O 43 I/O 44 I/O 45 I/O 46 I/O 47 GND I/O 48
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
176-TQFP/2128VL
1. NC pins are not to be connected to any active signals, VCC or GND.
13
Specifications ispLSI 2128VL
Pin Configuration
ispLSI 2128VL 160-Pin PQFP Pinout Diagram
I/O 112 GND I/O 111 I/O 110 I/O 109 I/O 108 I/O 107 I/O 106 I/O 105 I/O 104 I/O 103 I/O 102 I/O 101 I/O 100 I/O 99 I/O 98 I/O 97 I/O 96 VCC IN 5 TDO/IN 2 GND I/O 95 I/O 94 I/O 93 I/O 92 I/O 91 I/O 90 I/O 89 I/O 88 I/O 87 I/O 86 I/O 85 I/O 84 I/O 83 I/O 82 I/O 81 I/O 80 GND I/O 79 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121
I/O 113 VCC I/O 114 I/O 115 I/O 116 I/O 117 I/O 118 I/O 119 I/O 120 I/O 121 I/O 122 I/O 123 I/O 124 I/O 125 I/O 126 I/O 127 IN 7 Y0 RESET VCC GOE 1 GND BSCAN TDI/IN 0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 VCC I/O 14
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
ispLSI 2128VL
Top View
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/O 78 VCC I/O 77 I/O 76 I/O 75 I/O 74 I/O 73 I/O 72 I/O 71 I/O 70 I/O 69 I/O 68 I/O 67 I/O 66 I/O 65 I/O 64 IN 4 Y1 NC1 VCC GOE 0 GND Y2 TCK/IN 3 I/O 63 I/O 62 I/O 61 I/O 60 I/O 59 I/O 58 I/O 57 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 VCC I/O 49
1. NC pins are not to be connected to any active signal, VCC or GND.
I/O 15 GND I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 VCC TMS/IN 1 IN 6 GND I/O 32 I/O 34 I/O 34 I/O 35 I/O 36 I/O 37 I/O 38 I/O 39 I/O 40 I/O 41 I/O 42 I/O 43 I/O 44 I/O 45 I/O 46 I/O 47 GND I/O 48
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
160-PQFP/2128VL
14
Specifications ispLSI 2128VL
Signal Configuration
ispLSI 2128VL 100-Ball caBGA Signal Diagram
10
9
8
7
6
5
4
3
2
1
A B C D E F G H J K
I/O 39 I/O 37 I/O 35 I/O 32 NC1
I/O 41 I/O 40 I/O 38 I/O 36 IN 4
NC1
I/O 46 GND I/O 45 I/O 44 NC1
IN 5
VCC
I/O 50 I/O 54 NC1 I/O 62 I/O 2 NC1 I/O 12 I/O 13 VCC
I/O 52 I/O 56 NC1 I/O 63 Y0
I/O 55 I/O 58 I/O 60
RESET
I/O 57 I/O 59 I/O 61 IN 7
A B C D E F G H J K
I/O 43 I/O 42 NC1
TDO/ IN 2 I/O 47 NC1
I/O 49 I/O 51 I/O 53
I/O 33 Y2 I/O 31 NC1 I/O 24 I/O 20
I/O 48 Y1 I/O 21 I/O 19 I/O 17 GND
BSCAN
VCC
GOE 1 GND I/O 0 I/O 3 I/O 5 I/O 7
VCC TCK/ IN 3 I/O 29 I/O 27 I/O 25
GOE 0 GND I/O 28 I/O 26 I/O 23
I/O 34 I/O 30 NC1 I/O 22 I/O 18
I/O 16 NC1 I/O 15 TMS/ IN 1 IN 6
I/O 1 NC1 I/O 10 I/O 11 NC1
TDI/ IN 0 I/O 4 I/O 6 I/O 8 I/O 9
I/O 14
ispLSI 2128VL
Bottom View
10
1NCs
9
8
7
6
5
4
3
2
1
100-BGA/2128VL
are not to be connected to any active signals, VCC or GND.
Note: Ball A1 indicator dot on top side of package.
15
Specifications ispLSI 2128VL
Pin Configuration
ispLSI 2128VL 100-Pin TQFP Pinout Diagram
NC1 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 NC1 I/O 51 I/O 50 I/O 49 I/O 48 VCC IN 5 TDO/IN 2 GND I/O 47 I/O 46 I/O 45 I/O 44 NC1 I/O 43 I/O 42 I/O 41 I/O 40 I/O 39 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
I/O 57 I/O 58 I/O 59 1 NC I/O 60 I/O 61 I/O 62 I/O 63 IN 7 Y0 RESET VCC GOE 1 GND BSCAN TDI/IN 0 I/O 0 I/O 1 I/O 2 I/O 3 1 NC I/O 4 I/O 5 I/O 6 1 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
ispLSI 2128VL
Top View
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
NC1 I/O 38 I/O 37 I/O 36 NC1 I/O 35 I/O 34 I/O 33 I/O 32 IN 4 Y1 NC1 VCC GOE 0 GND Y2 TCK/IN 3 I/O 31 I/O 30 I/O 29 I/O 28 NC1 I/O 27 I/O 26 I/O 25
I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 1 NC I/O 12 I/O 13 I/O 14 I/O 15 VCC TMS/IN 1 IN 6 GND I/O 16 I/O 17 I/O 18 I/O 19 1 NC I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 1 NC
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100-TQFP/2128VL
1. NC pins are not to be connected to any active signals, VCC or GND.
16
Specifications ispLSI 2128VL
Part Number Description ispLSI 2128VL
Device Family Device Number Speed 150 = 150 MHz fmax 135 = 135 MHz fmax 100 = 100 MHz fmax
XXX X
XXXX X
Grade Blank = Commercial I = Industrial Package Q160 = 160-Pin PQFP T176 = 176-Pin TQFP B208 = 208-Ball fpBGA T100 = 100-Pin TQFP B100 = 100-Ball caBGA Power L = Low
0212/2128VL
ispLSI 2128VL Ordering Information
COMMERCIAL
FAMILY fmax (MHz) 150 150 150 150 150 135 135 ispLSI 135 135 135 100 100 100 100 100 tpd (ns) 6.0 6.0 6.0 6.0 6.0 7.5 7.5 7.5 7.5 7.5 10 10 10 10 10 I/Os 128 128 128 64 64 128 128 128 64 64 128 128 128 64 64 ORDERING NUMBER ispLSI 2128VL-150LT176 ispLSI 2128VL-150LQ160 ispLSI 2128VL-150LB208 ispLSI 2128VL-150LT100 ispLSI 2128VL-150LB100 ispLSI 2128VL-135LT176 ispLSI 2128VL-135LQ160 ispLSI 2128VL-135LB208 ispLSI 2128VL-135LT100 ispLSI 2128VL-135LB100 ispLSI 2128VL-100LT176 ispLSI 2128VL-100LQ160 ispLSI 2128VL-100LB208 ispLSI 2128VL-100LT100 ispLSI 2128VL-100LB100 PACKAGE 176-Pin TQFP 160-Pin PQFP 208-Ball fpBGA 100-Pin TQFP 100-Ball caBGA 176-Pin TQFP 160-Pin PQFP 208-Ball fpBGA 100-Pin TQFP 100-Ball caBGA 176-Pin TQFP 160-Pin PQFP 208-Ball fpBGA 100-Pin TQFP 100-Ball caBGA
Table 2-0041A/2128VL
INDUSTRIAL
FAMILY ispLSI fmax (MHz) 135 135 tpd (ns) 7.5 7.5 I/Os 64 128 ORDERING NUMBER ispLSI 2128VL-135LT100I ispLSI 2128VL-135LT176I PACKAGE 100-Pin TQFP 176-Pin TQFP
Table 2-0041B/2128VL
17

▲Up To Search▲

Price & Availability of ISPLSI2128VL-100LB100

	To Download ISPLSI2128VL-100LB100 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .